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ltc3708 1 3708fb typical application features applications description fast 2-phase, no r sense buck controller with output tracking n digital signal processors n network servers l , lt, ltc and ltm are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. high ef? ciency dual output step-down converter n very low duty factor operation (t on(min) < 85ns) n no r sense ? option for maximum ef? ciency n very fast transient response n programmable output voltage up/down tracking n 2-phase operation reduces input capacitance n 0.6v 1% output voltage reference n external frequency synchronization n monotonic soft-start n onboard high current mosfet drivers n wide v in range: up to 36v n adjustable cycle-by-cycle current limit n instant output overvoltage protection n optional short-circuit shutdown timer n power good output with 100s masking n available in 5mm 5mm qfn package the ltc ? 3708 is a dual, 2-phase synchronous step-down switching regulator with output voltage up/down tracking capability. the ic allows either coincident or ratiometric tracking. multiple ltc3708s can be daisy-chained in ap- plications requiring more than two voltages to be tracked. power supply sequencing is accomplished using an external soft-start timing capacitor. the ltc3708 uses a constant on-time, valley current mode control architecture to deliver very low duty factors without requiring a sense resistor. operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. an internal phase-locked loop allows the ic to be synchronized to an external clock. fault protection is provided by an output overvoltage comparator and an optional short-circuit shutdown timer. the regulator current limit level is user programmable. a wide supply range allows voltages as high as 36v to be stepped down to 0.6v output. 1f 100k 4.7f 5v 10 tg1 boost1 sw1 sense1 + bg1 sense1 C pgnd1 v fb1 track2 i on1 i th1 intlpf run/ss v cc drv cc ltc3708 pgood tg2 boost2 sw2 sense2 + 0.22f 0.22f m2 m1 b340a b340a v out1 2.5v 15a 19.1k 12.1k v in 10k 1k v in 33k 6.04k 6.04k 6.04k 1.5m 25k 100k 5v poscap 330f 4v s 2 l1 1.4h l2 1.2h m3 m4 12.1k f in sense2 C pgnd2 v fb2 fcb i on2 i th2 extlpf track1 sgnd v rng1 v rng2 bg2 0.1f 0.01f 0.1f 180pf 0.01f 1m 0.01f l1: panasonic etqp3hir4bf l2: panasonic etqp2hir2bf m1, m2: renesas hat2168 m3, m4: renesas hat2165 33k 180pf 3708 ta01 v out2 1.8v 15a poscap 470f 2.5v s 2 10f 50v s 4 v in 3.3v to 28v + + + 2ms/div 3708 ta01b v out2 (0.5v/div) v out1 (0.5v/div) load current (a) 80 efficiency (%) power loss (w) 90 100 75 85 95 0.01 1 10 3708 ta01c 70 4.5 7.5 9.0 3.0 1.5 6.0 0 0.1 20v in to 2.5v out 5v in to 2.5v out 20v in to 1.8v out 5v in to 1.8v out
ltc3708 2 3708fb pin configuration absolute maximum ratings (note 1) 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1run/ss i th1 v fb1 track1 sgnd track2 v fb2 i th2 sense1 ? pgnd1 bg1 drv cc bg2 pgnd2 sense2 ? v cc v rng1 fcb pgood i on1 boost1 tg1 sw1 sense1 + extlpf intlpf v rng2 i on2 boost2 tg2 sw2 sense2 + t jmax = 125c, ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3708euh#pbf ltc3708euh#trpbf 3708 32-lead (5mm 5mm) plastic qfn ?40c to 85c lead based finish tape and reel part marking package description temperature range ltc3708euh ltc3708euh#tr 3708 32-lead (5mm 5mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ input supply voltage (v cc , drv cc ) ............. 7v to ?0.3v boosted topside driver supply voltage boost1, 2 ............................................ 42v to ?0.3v switch voltage (sw1, 2) .............................. 36v to ?5v sense1 + , sense2 + voltages ....................... 36v to ?5v sense1 ? , sense2 ? voltages .................... 10v to ?0.3v i on1 , i on2 voltages .................................... 21v to ?0.3v (boost ? sw) voltages .............................. 7v to ?0.3v run/ss, pgood voltages .......................... 7v to ?0.3v pgood dc current ................................................. 5ma track1, track2 voltages ..............v cc + 0.3v to ?0.3v v rng1 , v rng2 voltages .................... v cc + 0.3v to ?0.3v i th1 , i th2 voltages.................................... 2.7v to ?0.3v v fb1 , v fb2 voltages .................................. 2.7v to ?0.3v intlpf, extlpf voltages ......................... 2.7v to ?0.3v fcb voltages ............................................... 7v to ?0.3v operating temperature range (note 5).... ?40c to 85c junction temperature (note 2) ........................... 125c storage temperature range ................... ?65c to 125c re? ow peak body temperature ........................... 260c electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, drv cc = 5v, unless otherwise noted. symbol parameter conditions min typ max units main control loop i q input dc supply current normal shutdown 2.4 250 3 400 ma a i fb1,2 feedback pin input current i th = 1.2v (notes 3, 4) ?50 ?100 na v ref internal reference voltage i th = 1.2v, 0c to 85c (notes 3, 4) i th = 1.2v (notes 3, 4) l 0.594 0.591 0.600 0.600 0.606 0.609 v v v fb1,2 feedback voltage i th = 1.2v (note 3) 0.594 0.600 0.606 v v fb(linereg)1,2 feedback voltage line regulation v cc = 4.5v to 6.5v (note 3) 0.02 %/v
ltc3708 3 3708fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, drv cc = 5v, unless otherwise noted. symbol parameter conditions min typ max units v fb(loadreg)1,2 feedback voltage load regulation i th = 0.5v to 1.9v (note 3) C0.05 C0.2 % g m(ea)1,2 error ampli? er transconductance i th = 1.2v (note 3) l 1.2 1.45 1.7 ms t on1,2 on-time i on = 60a, v fcb = 0v i on = 30a, v fcb = 0v 94 186 116 233 138 280 ns ns t on(min)1,2 minimum on-time i on = 180a 50 85 ns t off(min)1,2 minimum off-time i on = 30a 270 350 ns v sense(max)1,2 maximum current sense threshold v rng = 1v, v fb = 0.565v v rng = 0v, v fb = 0.565v v rng = vcc, v fb = 0.565v 125 90 180 143 100 200 160 110 220 mv mv mv v sense(min)1,2 minimum current sense threshold v rng = 1v, v fb = 0.635v v rng = 0v, v fb = 0.635v v rng = v cc , v fb = 0.635v C62 C42 C88 mv mv mv v fb(ov)1,2 overvoltage fault threshold 8.5 10 11.5 % v fb(uv)1,2 undervoltage fault threshold C380 C420 C460 mv v run/ss(on) run pin start threshold l 0.8 1.3 1.8 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 2.6 3 3.3 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 2.2 2.5 2.8 v i run/ss(c) soft-start charge current v run/ss = 0v C0.5 C1.2 C2 a i run/ss(d) soft-start discharge current v run/ss = v run/ss(le) , v fb1,2 = 0v 0.8 2 3 a v cc(uvlo) undervoltage lockout v cc falling 3.2 3.6 v v cc(uvlor) undervoltage lockout release v cc rising 3.5 3.8 v tg r up1,2 tg driver pull-up on-resistance tg high (note 6) 2 tg r down1,2 tg driver pull-down on-resistance tg low (note 6) 2 bg r up1,2 bg driver pull-up on-resistance bg high (note 6) 3 bg r down1,2 bg driver pull-down on-resistance bg low (note 6) 1 tracking i track1,2 track pin input current i th = 1.2v, v track = 0.2v (note 3) C100 C150 na v fb(track1,2) feedback voltage at tracking v track = 0v, i th = 1.2v (note 3) v track = 0.2v, i th = 1.2v (note 3) v track = 0.4v, i th = 1.2v (note 3) C10 190 390 0 200 400 C10 210 410 mv mv mv pgood output v fbh1,2 pgood upper threshold either v fb rising 8.5 10 11.5 % v fbl1,2 pgood lower threshold either v fb falling C8.5 C10 C11.5 % v fb(hys)1,2 pgood hysteresis v fb returning 3 5 % v pgl pgood low voltage i pgood = 5ma 0.1 0.4 v i pgood pgood leakage current v pgood = 7v 1 a pg delay pgood delay v fb falling 100 s phase-locked loops v fcb(dc) forced continuous threshold measured with a dc voltage at fcb pin 1.9 2.1 2.3 v v fcb(ac) clock input threshold measured with a ac pulse at fcb pin 1 1.5 2 v i extlpf external phase detector output current sourcing capability sinking capability f fcb < f sw1 , v extlpf = 0v f fcb > f sw1 , v extlpf = 2.4 20 C20 a a
ltc3708 4 3708fb typical performance characteristics load transient on channel 1 load transient on channel 2 coincident tracking ratiometric tracking electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, drv cc = 5v, unless otherwise noted. symbol parameter conditions min typ max units i intlpf internal phase detector output current sourcing capability sinking capability f sw1 < f sw2 , v intlpf = 0v f sw1 > f sw2 , v intlpf = 2.4 20 C20 a a t on(pll)1 t on1 modulation range by external pll up modulation down modulation i on1 = 60a, v extlpf = 1.8v i on1 = 60a, v extlpf = 0.6v 186 233 58 80 ns ns t on(pll)2 t on2 modulation range by internal pll up modulation down modulation i on1 = 60a, v extlpf = 1.8v i on1 = 60a, v extlpf = 0.6v 186 233 58 80 ns ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliabilty and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: t j = t a + (p d ? 34c/w) note 3: the ltc3708 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). note 4: internal reference voltage is tested indirectly by extracting error ampli? er offset from the feedback voltage. note 5: the ltc3708e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 6: r ds(on) limit is guaranteed by design and/or correlation to static test. i out1 10a/div v out1 100mv/div 20s/div 3708 g01 v out2 100mv/div i out2 10a/div v out1 100mv/div 20s/div 3708 g02 v out2 100mv/div v out1 0.5v/div v out2 0.5v/div 2ms/div 3708 g03 v out1 0.5v/div v out2 0.5v/div 2ms/div 3708 g04
ltc3708 5 3708fb typical performance characteristics soft-start power loss vs input voltage power loss vs load current frequency vs input voltage frequency vs load current on-time vs i on current on-time vs temperature current sense threshold vs i th voltage v out1 2v/div v out2 2v/div run/ss 5v/div i l1 5a/div 50ms/div 3708 g05 input voltage (v) 5 0 power loss (w) 1 2 3 4 5 6 10 15 20 25 3708 g06 v out = 2.5v i out = 15a v out = 1.8v load (ma) 10 2.0 2.5 3.5 10000 3707 g07 1.5 1.0 100 1000 100000 0.5 0 3.0 power loss (w) v in = 5v v out = 2.5v v out = 1.8v input voltage (v) 5 frequency (khz) 200 220 25 3708 g08 180 160 10 15 20 260 240 i out = 15a i out = 0a external synchronization (any i out ) load current (a) 0 frequency (khz) 100 150 3708 g09 50 0 5 10 15 250 200 forced continuous mode external synchronization discontinuous mode i on current (a) 1 10 on-time (ns) 100 1000 10000 10 100 1000 3708 g10 temperature (c) C50 0 on-time (ns) 50 100 150 200 050 100 150 3708 g11 250 300 C25 25 75 125 i on = 30a i on = 60a i th voltage (v) 0 current sense threshold (mv) 100 200 300 2 3708 g12 0 C100 50 150 250 v rng = 2v 1.4v 1v 0.7v C50 C150 C200 0.5 1 1.5 2.5 0.5v
ltc3708 6 3708fb typical performance characteristics maximum current sense threshold vs v rng voltage maximum current sense threshold vs temperature load regulation (figure 13 circuit) error ampli? er g m vs temperature sense pin input current vs temperature run/ss pin current vs temperature feedback voltage vs run/ss (soft-start) run/ss latch-off thresholds vs temperature undervoltage lockout threshold vs temperature v rng voltage (v) 0.5 350 300 250 200 150 100 50 0 1.25 1.75 3708 g13 0.75 1 1.5 2 maximum current sense threshold (mv) temperature (c) C50 maximum current sense threshold (mv) 140 150 160 25 75 150 3708 g14 130 120 110 C25 0 50 100 125 v rng = 1v load current (a) 0 C0.2 C0.1 0 12 3708 g15 C0.3 C0.4 369 15 C0.5 C0.6 C0.7 $ v out (%) forced continuous mode discontinuous mode temperature (c) C50 1.0 g m (ms) 1.1 1.2 1.3 1.4 050 100 150 3708 g16 1.5 1.6 C25 25 75 125 temperature (c) C50 50 i sense (a) 60 80 90 100 150 120 0 50 75 3708 g17 70 130 140 110 C25 25 100 125 150 i sense + i sense C temperature (c) C50 C25 C2 run/ss pin current (a) 0 3 0 50 75 3708 g18 C1 2 1 25 100 125 pull-up current pull-down current run/ss voltage (v) 1 700 600 500 400 300 200 100 0 1.75 2.25 3708 g19 1.25 1.5 2 2.5 v fb (mv) temperature (c) C50 2.0 run/ss threshold (v) 2.5 3.0 3.5 4.0 C25 0 25 50 3708 g20 75 100 125 150 latchoff enable latchoff threshold temperature (c) C50 undervoltage lockout threshold (v) 3.5 4.0 4.5 25 75 150 3708 g21 3.0 2.5 2.0 C25 0 50 100 125
ltc3708 7 3708fb typical performance characteristics on-time vs extlpf voltage on-time vs intlpf voltage 2-phase operation extlpf voltage (v) 1 0 t on1 (ns) 50 150 200 250 500 350 1.1 1.2 3708 g22 100 400 450 300 1.3 1.4 i on1 = 30a i on1 = 60a intlpf voltage (v) 0.6 0 t on2 (ns) 50 150 200 250 500 350 1 1.4 1.6 3708 g23 100 400 450 300 0.8 1.2 1.8 2.0 i on2 = 30a i on2 = 60a i in 2a/div v sw1 10v/div v sw2 10v/div v in 200mv/div 1s/div v in = 15v v out1 = 5v v out2 = 3.3v i out5 = i out3 = 2a 3708 g024 load transient response without external synchronization i out1 10a/div sw1 10v/div 10s/div 3708 g25 v out1 50mv/div f s = 200khz f s = 240khz load transient response with external synchronization i out1 10a/div sw1 10v/div 10s/div 3708 g26 v out1 50mv/div f s = 220khz f s = 220khz discontinuous mode operation power good mask i l 0.5a/div v out 20mv/div 2s/div v in = 15v v out = 5v v fcb = 5v i out = 20ma 3708 g027 v fb 0.2v/div 100s/div 3708 g28 pgood 2v/div
ltc3708 8 3708fb pin functions run/ss (pin 1): run control and soft-start input. a capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.5s/f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the ltc3708. i th1 , i th2 (pins 2, 8): error ampli? er compensation point and current control threshold. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). v fb1 , v fb2 (pins 3, 7): error ampli? er feedback input. this pin connects the error ampli? er input to an external resistive divider from v out . additional compensation can be implemented, if desired, using this pin. track1, track2 (pins 4, 6): tie track2 pin to a re- sistive divider connected to the output of channel 1 for either coincident or ratiometric output tracking. track1 is used in the same manner between multiple ltc3708s (see applications information). to disable this feature, tie the pins to v cc . do not float these pins. sgnd (pins 5, 33): signal ground. all small-signal com- ponents and compensation components should connect to this ground and eventually connect to pgnd at one point. the exposed pad of the ltc3708euh must be soldered to the pcb. extlpf (pin 9): filter connection for the external pll. this pll is used to synchronize the ltc3708 to an external clock. if external clock is not used, leave this pin ? oating. intlpf (pin 10): filter connection for the internal pll. this pll is used to phase shift the second channel to the ? rst channel by 180. v cc (pin 17): main input supply. decouple this pin to sgnd with an rc ? lter (10, 1f for example). drv cc (pin 21): driver supply. provides supply to the drivers for the bottom gates. also used for charging the bootstrap capacitors. bg1, bg2 (pins 22, 20): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and drv cc . pgnd1, pgnd2 (pins 23, 19): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c drvcc and the (C) terminal of c in . sense1C, sense2C (pins 24, 18): current sense com- parator input. the (C) input to the current comparator is used to accurately kelvin sense the bottom side of the sense resistor or mosfet. sense1 + , sense2 + (pins 25, 16): current sense com- parator input. the (+) input to the current comparator is normally connected to the sw node unless using a sense resistor (see applications information). sw1, sw2 (pins 26, 15): switch node. the (C) terminal of the bootstrap capacitor c b connects here. this pin swings from a schottky diode voltage drop below ground up to v in . tg1, tg2 (pins 27, 14): top gate drive. drives the top n-channel mosfet with a voltage swing equal to drv cc superimposed on the switch node voltage sw. boost1, boost2 (pins 28, 13): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below drv cc up to v in + drv cc . i on1 , i on2 (pins 29, 12): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. pgood (pin 30): power good output. open-drain logic output that is pulled to ground when either or both output voltages are not within 10% of the regulation point. the output voltage must be out of regulation for at least 100s before the power good output is pulled to ground. fcb (pin 31): forced continuous and external clock input. tie this pin to ground to force continuous synchronous operation or to v cc to enable discontinuous mode opera- tion at light load. feeding an external clock signal into this pin will synchronize the ltc3708 to the external clock and enable forced continuous mode. v rng1 , v rng2 (pins 32, 11): sense voltage range input. the voltage at this pin is ten times the nominal sense volt- age at maximum output current and can be programmed from 0.5v to 2v. the sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to v cc .
ltc3708 9 3708fb functional diagram clock detector fcb intlpf i on r on extlpf phase detector (pd1) to channel 2 ost fcnt on shdn ov enable phase detector (pd2) ost from channel 2 tg t on = (10pf) 0.7 i ion r s 20k q C + C + C + C + C + i cmp i rev tg c b m1 l1 v in d b v out + c in switch logic sw sense + drv cc bg pgnd sense C 0.66v 0.54v from channel 2 ov and uv comparators v fb r2 sgnd boost m2 v cc c vcc 0.6v ref c drvcc + c out r1 pgood ov uv run shdn enable >100s blanking v rng 1.4v 0.7v i th c c r c track q4 ea 3.3a s 1 240k q1 q2 q3 0.6v v ref duplicate for second channel controller note: the run/ss pin only clamps v ref for phase 1 not phase 2. + C + C 1.3v run/ss 1.2a 6v 3708 fd c ss 1.3v c epll r epll r ipll c ipll
ltc3708 10 3708fb operation (refer to functional diagram) main control loop the ltc3708 uses a constant on-time, current mode step- down architecture with two control channels operating at 180 degrees out of phase. in normal operation, each top mosfet is turned on for a ? xed interval determined by its own one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and repeating the cycle. the trip level of the current comparator is set by the i th voltage which is the output of each error ampli? er, ea. inductor current is determined by sensing the voltage between the sense C and sense + pins using either the bottom mosfet on-resistance or a separate sense resistor. at low load currents, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev , which then shuts off m2 resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinuous mode operation is disabled when the fcb pin is brought below 1.9v, forcing continuous synchronous operation. the main control loop is shut down by pulling the run/ss pin low, turning off both m1 and m2. releasing the pin al- lows an internal 1.2a current source to charge an external soft-start capacitor, c ss . when this voltage reaches 1.3v, the controller turns on and begins switching, but with the effective reference voltage clamped at 0v. as c ss continues to charge, the effective reference ramps up at the same rate and controls the rise rate of the output voltage. operating frequency the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on-time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . when the ltc3708 is synchronized to an external clock, the operating frequency will then be solely determined by the external clock. output overvoltage protection an overvoltage comparator ov guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in this condition, m1 is turned off and m2 is turned on and held on until the condition is cleared. short-circuit detection and protection after the controller has been started and given adequate time to charge the output capacitors, the run/ss capacitor is used as the short-circuit time-out capacitor. if either one of the output voltages falls to less than 70% of its nominal output voltage, the run/ss capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, both controllers will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing >5a pull-up at a compli- ance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of the run/ss capacitor during an overcurrent and/or short- circuit condition. power good (pgood) pin overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback volt- age exceeds a 10% window around the regulation point. in addition, the output feedback voltage must be out of this window for a continuous duration of at least 100s before pgood is pulled low. this is to prevent any glitch on the feedback voltage from creating a false power bad signal. the pgood will indicate high immediately when the feedback voltage is in regulation.
ltc3708 11 3708fb operation (refer to functional diagram) drv cc power for the top and bottom mosfet drivers is derived from the drv cc pin. the top mosfet driver is powered from a ? oating bootstrap capacitor, c b . this capacitor is normally recharged from drv cc through an external schottky diode, d b , when the top mosfet is turned off. 2-phase operation for the ltc3708 to operate optimally as a 2-phase controller, the resistors connected to the i on pins must be selected such that the free-running frequency of each channel is close to that of the other. an internal phase-locked loop (pll) will then ensure that channel 2 operates at the same frequency as channel 1, but phase shifted by 180. the loop ? lter connected to the intlpf pin provides stability to the pll. for external clock synchronization, a second pll is incorporated to adjust the on-time of channel 1 until its frequency is the same as the external clock. compensation for the external pll is through the extlpf pin. the loop ? lter components tied to the intlpf and extlpf pins are used to compensate the internal ppl and external pll respectively. the typical value ranges are: intlpf: r ipll = 2k to 10k, c ipll = 10nf to 100nf extlpf: r epll 1k, c epll = 10nf to 100nf for noise suppression, a capacitor with a value of 1nf or less should be placed from intlpf to ground and extlpf to ground. the ltc3708s 2-phase operation brings considerable bene? ts to portable applications and automatic electron- ics. it lowers the input ? ltering requirement, reduces electromagnetic interference (emi) and increases the power conversion ef? ciency. until the introduction of the 2-phase operation, dual switching regulators operated both channels in phase (i.e., single phase operation). this means that both controlling switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor or battery. such operation results in higher input rms current, larger and/or more expensive input capacitors, more power loss and worse emi in the input source (whether a wall adapter or a battery). in contrast to single phase operation, the two channels of a 2-phase switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a signi? cant reduc- tion in total rms input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for emi and improves real world operating ef? ciency. figure 1 compares the input waveforms for a representative single phase dual switching regulator to the 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2-phase dropped the input current from 2.53a rms to 1.55a rms . figure 1. input waveforms comparing single phase (1a) and 2-phase (1b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div i in(meas) = 2.53a rms i in(meas) = 1.55a rms (1a) (1b) 3708 f01
ltc3708 12 3708fb operation (refer to functional diagram) while this is an impressive reduction in itself, remember that the power losses are proportional to i 2 rms , meaning that the actual power wasted is reduced by a factor of 2.66. the reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage, v in . figure 2 shows how the rms input current varies for single phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase opera- tion are not just limited to a narrow operating range, but in input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3708 f02 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a figure 2. rms input current comparison fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitance requirement to that for just one channel operating at maximum current and 50% duty cycle.
ltc3708 13 3708fb applications information the basic ltc3708 application circuit is shown on the ? rst page of this data sheet. external component selection is primarily determined by the maximum load current and begins with the selection of the power mosfet switches and/or sense resistor. for the ltc3708, the inductor cur- rent is determined by the r ds(on) of the synchronous mosfet or by a sense resistor when the user opts for more accurate current sensing. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple speci? cation. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across the r ds(on) of the synchronous mosfet or through a sense resistor that appears between the sense + and sense C pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately v rng /7. the current mode control loop will not allow the inductor current valleys to exceed v rng /(7 ? r sense ). in practice, one should allow some margin for variations in the ltc3708 and external component values. a good guide for selecting the sense resistance is: r v i sense rng out max = 10 ? () the voltage of the v rng pin can be set using an external resistive divider from v cc between 0.5v and 2v, resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to ground or v cc , in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense voltage is about 1.4 times this nominal value. connecting the sense + and sense C pins the ltc3708 provides the user with an optional method to sense current through a sense resistor instead of using the r ds(on) of the synchronous mosfet. when using a sense resistor, it is placed between the source of the syn- chronous mosfet and ground. to measure the voltage across this resistor, connect the sense + pin to the source of the synchronous mosfet and the sense C pin to the other end of the resistor. the sense + and sense C pins provide the kelvin connections, ensuring accurate voltage measurement across the resistor. using a sense resistor provides a well-de? ned current limit, but adds cost and reduces ef? ciency. alternatively, one can use the synchro- nous mosfet as the current sense element by simply connecting the sense + pin to the switch node sw and the sense C pin to the source of the synchronous mosfet, eliminating the sense resistor. this improves ef? ciency, but one must carefully choose the mosfet on-resistance as discussed below. power mosfet selection each output stage of the ltc3708 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance, c rss , and maximum current, i ds(max) . the gate drive voltage is set by the 5v drv cc supply. consequently, logic-level threshold mosfets must be used in ltc3708 applications. if the drivers voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on-re- sistance. mosfet on-resistance is typically speci? ed with a maximum value r ds(on)(max) at 25c. additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = the t term is a normalization factor (unity at 25c) ac- counting for the signi? cant variation in on-resistance with temperature, typically about 0.4%/c. for a maximum junction temperature of 100c, using a value 100c = 1.3 is reasonable (see figure 3).
ltc3708 14 3708fb applications information the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and the load current. when the ltc3708 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = ? the resulting power dissipation in the mosfets at maxi- mum output current are: pdi r vi c f r drv v v pdi r top top out max t top ds on in out max rss dr cc gs th gs th bot bot out max t bot ds on =+ () + ? ? ? ? ? ? = ??? (.)? ? ? ? ? ? ? ??? () () () () () () () () () 2 2 2 05 11 both mosfets have i 2 r losses and the top mosfet in- cludes an additional term for transition losses, which are largest at high input voltages. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. operating frequency the choice of operating frequency is a trade-off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching and driving losses but requires larger inductance and/or ca- pacitance to maintain low output ripple voltage. the operating frequency of ltc3708 applications is deter- mined implicitly by the one-shot timer that controls the on time, t on , of the top mosfet switch. the on time is set by the current into the i on pin according to: t i pf on ion = () 07 10 . tying a resistor, r on , from v in to the i on pin yields an on time inversely proportional to v in . for a step-down converter, this results in approximately constant frequency operation as the input supply varies: f v rpf out on = () 07 10 .? figure 4 shows how r on relates to switching frequency for several common output voltages. junction temperature (c) C50 r t normalized on-resistance 1.0 1.5 150 3708 f03 0.5 0 0 50 100 2.0 figure 3. r ds(on) vs temperature r on (k) 100 100 switching frequency (khz) 1000 1000 10000 3708 f04 v out = 3.3v v out = 1.5v v out = 2.5v figure 4. switching frequency vs r on
ltc3708 15 3708fb applications information pll and frequency synchronization in the ltc3708, there are two onboard phase-locked loops (pll). one pll is used to achieve frequency locking and 180 phase shift between the two channels while the sec- ond pll locks onto the rising edge of an external clock. since the ltc3708 uses a constant on-time architecture, the error signal generated by the phase detector of the pll is used to vary the on time to achieve frequency locking and phase separation. the variable on-time range is from 0.5 ? t on to 2 ? t on , where t on is the initial on time set by the r on resistor. to fully utilize the frequency synchronization range of the pll, it is advisable to set the initial on time properly so that the two channels have close free-running frequencies. frequencies far apart may exceed the synchronization capability of the pll. if the two output voltages are v out1 and v out2 , for example, r on resistors should then be selected proportionally: r r v v on on out out 1 2 1 2 = similarly, if the external pll is engaged to synchronize to an external frequency of f ext , r on1 should be selected close to: r v fpf v fpf on out ext out ext 1 1 2 07 10 07 10 = = ? ? ? ? ? ? .? ? .? ? hence, r on2 in this case, channel 1 will ? rst be synchronized to the external frequency and channel 2 will then be synchronized to channel 1 with 180 phase separation. inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: = ? ? ? ? ? ? ? ? ? ? ? ? i v fl v v l out out in ? C 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and ripples in the output voltage. highest ef? ciency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size and ef? ciency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a speci? ed maximum, the induc- tance should be chosen according to: l v fi v v out lmax out in max = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida and panasonic. schottky diode selection the schottky diodes in parallel with both bottom mosfets conduct during the dead time between the conduction of the power mosfet switches. they are intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which causes a modest (about 1%) ef? ciency loss. the diodes can be rated for about one-half to one-? fth of the full load current since they are on for only a fraction of the duty cycle. in order for the diodes to be effective, the inductance between them and the bottom mosfets must be as small as possible, mandating that these components be placed as close as possible in the circuit board layout. the diodes can be omitted if the ef? ciency loss is tolerable. c in and c out selection the selection of c in is simpli? ed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case rms current occurs when only one controller is operating. the controller with the
ltc3708 16 3708fb applications information highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms current requirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input rms ripple current from this maximum value (see figure 2). the type of input capacitor, value and esr rating have ef- ? ciency effects that need to be considered in the selection process. the capacitance value chosen should be suf? cient to store adequate charge to keep pulsating input currents down. 20f to 40f is usually suf? cient for a 25w output supply operating at 200khz. the esr of the capacitor is important for capacitor power dissipation as well as overall ef? ciency. all of the power (rms ripple current 2 ? esr) not only heats up the capacitor but wastes power from the battery. medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coef? cients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolyt- ics higher esr and dryout possibility require several to be used. 2-phase systems allow the lowest amount of capacitance overall. as little as one 22f or two to three 10f ceramic capacitors are an ideal choice in a 20w to 35w power supply due to their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for highest ef? ciency battery operated systems. also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the current of the top n-channel mosfet is approximately a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: ii vvv v rms max out in out in ? () ? ? ? ? 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the bene? t of the ltc3708 2-phase operation can be calculated by using the equation above for the higher power channel and then calculating the loss that would have resulted if both controller channels switch on at the same time. the total rms power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. remember that input protection fuse resistance, battery resistance and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall bene? t of a 2-phase design will only be fully realized when the source impedance of the power supply/battery is included in the ef? ciency testing. the drains of the two top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce un- desirable voltage and current resonances at v in . the selection of c out is driven by the effective series resistance (esr) required to minimize voltage ripple and load step transients. the output ripple ( v out ) is determined by: ? v i esr fc out l out + ? ? ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance, and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering and has the necessary rms current rating.
ltc3708 17 3708fb applications information manufacturers such as nichicon, united chemi-con and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet the esr, rms current handling and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. special polymer capacitors offer very low esr but have lower storage capacity per unit volume than other capacitor types. these capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capaci- tors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. a typical application will require several to many aluminum electrolytic capacitors in paral- lel. a combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. other capacitor types include nichicon pl series, sanyo poscap , nec neocap, cornell dubilier esre and sprague 595d series. consult manufacturers for other speci? c recommendations. top mosfet driver supply (c b , d b in the functional diagram) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from drv cc when the switch node is low. note that the average voltage across c b is approximately drv cc . when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + drv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1f to 0.47f is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 2.3v threshold (typically to v cc ) enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. the load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and the ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. tying the fcb pin below 1.9v forces continuous synchro- nous operation, allowing current to reverse at light loads and maintaining high frequency operation. besides providing a logic input to force continuous op- eration, the fcb pin acts as the input for external clock synchronization. upon detecting the presence of an ex- ternal clock signal, channel 1 will lock on to this external clock and this will be followed by channel 2 (see pll and frequency synchronization). the ltc3708 defaults to forced continuous mode when sychronized to an external clock or when the pgood signal is low. fault conditions: current limit the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3708, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+ () () ? ? 1 2
ltc3708 18 3708fb applications information the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambient temperature, conditions which cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed junction temperature and the resulting value of i limit , which heats the junction. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on-resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. for a more accurate current limiting, a sense resistor can be used. sense resistors in the 1w power range can be easily available in the 5%, 2% or 1% tolerance. the temperature coef? cient of these resistors is very low, ranging from 250ppm/c to 75ppm/c. in this case, the (r ds(on) ? t ) product in the above equation can simply be replaced by the r sense value. minimum off time and dropout operation the minimum off time t off(min) is the smallest amount of time that the ltc3708 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 270ns. the minimum off time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + a plot of maximum frequency vs duty cycle is shown in figure 5. soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltc3708 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v shuts down the ltc3708. releasing the pin allows an internal 1.2a in- ternal current source to charge the external capacitor, c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss == () 13 12 11 . . ?./ when the run/ss voltage reaches the on threshold (typically 1.3v), the ltc3708 begins operating with a clamp on channel 1s reference voltage. the clamp level is one threshold voltage below run/ss. as the voltage on run/ss continues to rise, channel 1s reference is raised at the same rate, achieving monotonic output voltage soft-start (figure 6). when run/ss rises 0.6v above the on threshold, the reference clamp is invalidated and the internal precision reference takes over. when channel 2 is tracked to channel 1, soft-start on channel 2 is automati- cally achieved (see output voltage tracking). 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 3708 f05 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) figure 5. maximum switching frequency vs duty cycle
ltc3708 19 3708fb applications information controlled soft-start requires that the timing capacitor, c ss , be made large enough to guarantee that the output can track the voltage rise on the run/ss pin. the minimum c ss capacitance can be calculated: c rr r ar v c ss sense rng out > + 12 1 30 ? ? ? where r1 and r2 are the feedback resistive dividers (functional diagram), c out is the output capacitance and r sense is the current sense resistance. when bottom mosfet r ds(on) is used for current sensing, r sense should be replaced with the worst-case r ds(on)(max) . generally, 0.1f is more than suf? cient for c ss . after the controller has been started and given adequate time to charge the output capacitor, c ss is used as a short- circuit timer. after the run/ss pin charges above 3v and if either output voltage falls below 70% of its regulated value, a short-circuit fault is assumed. a 2a current then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 2.5v, the controller turns off all power mosfets, shutting down both channels. the run/ss pin must be actively pulled down to ground in order to restart operation. overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. this feature can be overridden by adding a pull-up cur- rent of >5a to the run/ss pin (figure 7). the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. output voltage tracking the ltc3708 allows the user to program how the second channel output ramps up and down by means of the track2 pin. through this pin, the second channel output can be set up to either coincidently or ratiometrically track the channel 1 output, as shown in figure 8. similar to run/ss, the track2 pin acts as a clamp on channel 2s reference voltage. v out2 is referenced to the track2 voltage when the track2 < 0.6v and to the internal precision reference when track2 > 0.6v. to implement the tracking in figure 8a, connect an extra resistive divider to the output of channel 1 and connect its midpoint to the track2 pin. the ratio of this divider should be selected the same as that of channel 2s feedback divider (figure 9a). in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 8b, no extra divider is needed; simply connect the track2 pin to the v fb1 pin (figure 9b). by selecting different resistors, the ltc3708 can achieve different modes of tracking including the two in figure 8. so which mode should be programmed? while either mode in figure 8 satis? es most practical applications, there does exist some trade-off. the ratiometric mode saves a pair of resistors but the coincident mode offers better output regulation. this can be better understood with the help of figure 10. at the input stage of channel 2s error ampli? er, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the track2 voltage is substantially higher than 0.6v at steady state and effectively turns off run/ss 3708 f06 v out1 time time on threshold $ v = 0.6v figure 6. monotonic soft-start waveforms 3.3v or 5v run/ss v in d1 on c ss r ss * *optional to override overcurrent latchoff 3708 f07 figure 7. run/ss pin interfacing with latchoff defeated
ltc3708 20 3708fb applications information d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.6v reference. in the ratiometric mode, however, track2 equals 0.6v even at steady state. d1 will divert part of the bias current and make v fb2 slightly lower than 0.6v. although this error is minimized by the exponential i-v characteristic of the diodes, it does impose a ? nite amount of output voltage deviation. further, when channel 1s output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. the number of resistors in figure 9a can be further reduced with the scheme in figure 11. in a system that requires more than two tracked supplies, multiple ltc3708s can be daisy-chained through the track1 pin. track1 clamps channel 1s reference in the same manner track2 clamps channel 2. to eliminate the possibility of multiple ltc3708s coming on at different times, only the master ltc3708s run/ss pin should be time (8a) coincident tracking v out1 v out2 output voltage time 3708 f08 (8b) ratiometric tracking v out1 v out2 output voltage figure 8. two different modes of output voltage tracking r3 r1 r4 r2 r3 v out2 r4 (9a) coincident tracking setup to v fb1 pin to track2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3708 f09 (9b) ratiometric tracking setup to v fb1 pin to track2 pin to v fb2 pin v out1 figure 9. setup for coincident and ratiometric tracking r r v r r v out out 1 206 1 3 406 1 12 =?= ? ? ? ? ? ? ? . , . C + ii d1 track2 0.6v v fb2 d2 d3 3708 f10 ea2 figure 10. equivalent input circuit of error ampli? er of channel 2
ltc3708 21 3708fb applications information connected to a soft-start capacitor. all other ltc3708s should have their run/ss pins pulled up to v cc with a resistor between 50k and 300k. figure 12 shows the circuit with four outputs. three of them are programmed in the coincident mode while the fourth one tracks ratiometrically. if output tracking is not needed, connect the track pins to v cc . do not float these pins. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3708 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the ef? ciency to drop at high output currents. in continuous mode, the average output current ? ows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 and r l = 0.005, the loss will range from 15mw up to 1.5w as the output current varies from 1a to 10a. r1 r4 v out1 v out2 to track2 pin to v fb1 pin to v fb2 pin r2 r5 r3 3708 f11 figure 11. alternative setup for coincident tracking rr r v r rr r r v out out 12 306 1 1 23 4 506 1 12 + = + == ? ? . C, . ? ? ? ? ? ? track1 v fb1 c ss r3 r1 r2 r5 v out1 r2 r4 r2 r2 v fb2 to v cc to v cc v out2 r5 r2 v out4 r4 100k r2 v out3 run/ss track2 ltc3708 master track1 v fb1 v fb2 run/ss track2 ltc3708 slave (12a) circuit setup time 3708 f12 (12b) output voltage v out1 v out3 v out4 v out2 output voltage figure 12. four outputs with tracking and ratiometric sequencing r r v r r v r r v out out out 1 206 1 3 206 1 4 20 12 3 =?= ?= . , . , .. , . 6 1 5 206 1 4 ?= ? ? ? ? ? ? ? r r v out
ltc3708 22 3708fb applications information 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capaci- tance, among other factors. the loss is signi? cant at input voltages above 20v and can be estimated from: transition loss vi c f r drv v v in out rss ds on drv cc gs th gs th ? + ? ? ? ? ? ? (.)? ? ? ? ? ()_ () () 05 11 2 3. drv cc and v cc current. this is the sum of the mosfet driver and control currents. the driver current supplies the gate charge q g required to switch the power mosfets. this current is typically much larger than the control circuit current. in continuous mode operation: i gatechg = f(q g(top) + q g(bot) ) 4. c in loss. the input capacitor has the dif? cult job of ? ltering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and suf? cient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. the ltc3708 2-phase architecture typically halves this c in loss over the single phase solutions. other losses, including c out esr loss, schottky conduc- tion loss during dead time and inductor core loss generally account for less than 2% additional loss. when making any adjustments to improve ef? ciency, the ? nal arbiter is the total input current for the regulator at your operating point. if you make a change and the input current decreases, then you improve the ef? ciency. if there is no change in input current, then there is no change in ef? ciency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problems. the i th pin external components shown in figure 13 will pro- vide adequate compensation for most applications. for a detailed explanation of switching control loop theory see linear technology application note 76. design example as a design example, take a supply with the following speci? cations: v in = 7v to 28v (15v nominal), v out1 = 2.5v, v out2 = 1.8v, i out1(max) = i out2(max) = 10a, f = 500khz and v out2 to track v out1 . first calculate the timing resistor: r v v khz pf k on1 25 0 7 500 10 714 = ()( )() = . . select a standard value of 715k. r v v khz pf k on2 18 0 7 500 10 514 = ()( )() = . . select a standard value of 511k. next, choose the feedback resistors: r r v v 1 2 25 06 1317 == . . ?. select r1 = 31.6k, r2 = 10k. r r v v 3 4 18 06 12 == . . ? select r3 = 20k, r4 = 10k. for v out2 to coincidently track v out1 at start-up, connect an extra pair of r3 and r4 across v out1 with its midpoint tied to the track2 pin.
ltc3708 23 3708fb applications information third, design the inductors for about 40% ripple current at the maximum v in : l v khz a v v h 1 25 500 0 4 10 1 25 28 11 = ()()() ? ? ? ? ? ? = . . ? . . a standard 1h inductor will result in 45% of ripple current (4.5a) at worst case. l v khz a v v h 2 18 500 0 4 10 1 18 28 08 = ()()() ? ? ? ? ? ? = . . ? . . l2 can also use 1h to save some bom (bill of material) cost; the resulting ripple current is 3.4a. the selection of mosfets is simpli? ed by the fact that both channels have the same maximum output current. select the top and bottom mosfets for one channel and the same mosfets can be used for the other. take channel 1 for calculation and begin with the bottom synchronous mosfet. as stated previously in the power mosfet se- lection section, the major criterion in selecting the bottom mosfet is low r ds(on) . choose an si4874 for example: r ds(on) = 0.0083 (nom) 0.010 (max), ja = 40c/w. the nominal sense voltage is: v sns(nom) = (10a)(1.3)(0.0083) = 108mv tying v rng1 to 1.1v will set the current sense voltage range for a nominal value of 110mv with the current limit occurring at 146mv. to check if the current limit is acceptable, assume a junction temperature of about 80c above a 70c ambient with 150c = 1.5: i mv aa limit () () + () = 146 15 0010 1 2 4 1 11 8 .. .. and double check the assumed t j in the mosfet: p vv v aw bot = ()() () = 28 2 5 28 11 8 1 5 0 010 1 9 2 ?. ... . t j = 70c + (1.90w)(40c/w) = 146 because the top mosfet is on for only a short time, an si4884 will be suf? cient: r ds(on) = 0.0165 (max), c rss = 190pf, v gs(th) = 1v, ja = 42c/w. checking its power dissipation at current limit with 130c = 1.6: p v v av a pf khz vv v www top = ()() () + ()( ) ()()( ) () + ? ? ? ? ? ? =+= 25 28 11 8 1 6 0 0165 0 5 28 11 8 190 500 2 1 51 1 1 033 110 143 22 . ... . . ? .. . t j = 70c + (1.43w)(42c/w) = 130 the junction temperatures for both top and bottom mosfets will be signi? cantly less at nominal current, but the above analysis shows that careful attention to pcb layout and heat sinking will be necessary in this circuit. the same mosfets (si4874 and si4884) can be used for channel 2. finally, an input capacitor is chosen for an rms current rating of about 5a at 85c and the output capacitors are chosen for a low esr of 0.013 to minimize output volt- age changes due to inductor ripple current and load steps. the ripple voltage will be only: =+ ? ? ? ? ? ? =+ ? ? ? ? ? ? = =+ ? ? ? ? ? ? =+ ? ? ? ? ? ? = v i esr fc a khz f mv v i esr fc a khz f mv out ripple l out out ripple l out 11 22 1 8 45 0013 1 8 500 470 60 1 8 34 0013 1 8 500 470 46 () () ? ?? .?. ?? ? ?? .?. ?? however, a 0a to 10a load step will cause an output change of up to: v out(step) = i load(esr) = (10a)(0.013) = 130mv an optional 22f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 13.
ltc3708 24 3708fb applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3708. these items are also illustrated graphically in figure 14. figure 15 further shows the current waveforms present in the various branches of the 2-phase synchronous buck regulators operating in the continuous mode. ? place the loop of m1, m3 and c in1 in a compact area. this loop conducts high pulsating current and its area needs to be minimized. place m2, m4 and c in2 in the same way. ? place c in1 and c in2 within the distance of 1cm. longer distance may cause a large resonant loop. ? connect the negative plates of c out1 and c dr1 to pgnd1 before it joins pgnd2 at the ground plane. connect c out2 and c dr2 in the same way so that power grounds are separated before they meet at a single point. ? cover the board area under the ltc3708 with a sgnd plane. for the ltc3708euh, solder the back of the ic to this plane. separate sgnd from the power ground and connect all signal components (i th , v fb , i on , v cc , extlpf, intlpf, v rng , track and run/ss) to the sgnd plane before it joins pgnd. connect sgnd to the gound plane at a single point. ? run sense + and sense C across the bottom mosfet (or r sense when a separate current sensing resistor is used) with kelvin connection (figure 16). route sense + and sense C together with minimum pc trace separation. the ? lter capacitor (when used) between sense + and sense C should be as close to the ltc3708 as possible. ? keep the high dv/dt nodes sw, tg and boost away from sensitive small-signal nodes. 1f 0.22f boost2 bat54a 10 4.7f pgnd1 1f 5v tg1 17 4 31 21 14 13 15 16 20 18 19 11 12 7 30 10 8 20k 0.01f 680pf 0.1f 10k 1% c in : united chemi-con thcr60eih106zt c out1 , c out2 : sanyo poscap 4tpd470m l1, l2: sumida cep125-1r0m m1, m2: vishay si4884 m3, m4: vishay si4874 56pf 5v pgood 100k 20k 1% 27 28 26 25 22 24 23 32 29 3 6 9 2 boost1 sw1 sense1 + bg1 sense1 C pgnd1 v rng1 v rng2 i on1 v fb1 track2 extlpf i th1 v cc track1 fcb drv cc ltc3708euh tg2 boost2 boost2 sw2 sense2 + 0.22f m2 m1 v out1 2.5v 10a v in 56pf 20k l1 1h pgnd1 l2 1h b340a m3 m4 sense2 C pgnd2 v rng2 v fb2 i on2 pwrgd intlpf i th2 run/ss sgnd bg2 680pf 100pf 15 0.01f 715k 31.6k 1% r2 10k 1% 20k 1% 10k 1% 10k 511k 39k v in v cc 11k 100pf 0.022f 1nf 3708 f13 1f v out1 1.8v 10a c out2 470f 4v 22f 6.3v x7r v cc b340a + c out1 470f 4v c in 10f 35v s 4 v in 7v to 28v 22f 6.3v x7r + + figure 13. design example: 2.5v/10a and 1.8v/10a at 500khz with output tracking
ltc3708 25 3708fb applications information ? connect the decoupling capacitors c dr1 and c dr2 close to the drv cc and pgnd pins. connect c b1 and c b2 close to the boost and sw pins. ? connect the decoupling capacitor c vcc right across the v cc pin and sgnd plane. connect the ea compensation components close to the i th pins. connect the pll loop ? lter close to the extlpf and intlpf pins. connect the i on decoupling capacitor close to the i on pins. ? flood all unused areas on all layers with copper. flooding will reduce the temperature rise of the power components. you can connect the copper area to any dc net (v in , v out , gnd or to any other dc rail in your system). v fb1 i th1 i on1 extlpf track1 v rng1 v cc 5v c vcc c dr1 c b1 5v c dr2 c ss sgnd run/ss v rng2 track2 intlpf i on2 i th2 v fb2 r on2 r on1 tg1 fcb pgood sw1 boost ltc3708 sense1 + sense1 C pgnd1 bg1 drv cc bg2 pgnd2 sense2 C sense2 + boost2 sw2 tg2 r1 r3 r4 r2 3708 f15 c out1 c out2 c b2 v in m3 c in1 c in2 d1 l1 l2 m1 m2 m4 d2 figure 14. ltc3708 layout diagram
ltc3708 26 3708fb applications information r l1 d1 l1 sw1 v out1 c out1 + v in ceramic c in r in + r l2 d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 3708 f15 v out2 c out2 + ceramic sense + sense C (16b) sensing a resistor 3708 f16 r sense sense + sense C (16a) sensing the bottom mosfet mosfet d d d d g s s s figure 15. branch current waveforms figure 16. kelvin sensing
ltc3708 27 3708fb applications information 1f 100k 4.7f 5v 10 tg1 boost1 sw1 sense1 + bg1 sense1 C pgnd1 v fb1 track2 i on1 i th1 intlpf run/ss v cc drv cc ltc3708 pgood tg2 boost2 sw2 sense2 + c b1 0.1f c b2 0.1f m2 m1 d b1 d b2 b340la b340la v out1 2.5v 15a 19.1k 1% 12.1k 1% v in 3.32k 470pf 475 v in 15k 6.04k 1% 6.04k 1% r on1 1.5m 24.9k 130k 5v c out1 330f 4v s 2 l1 1.43h l2 1.22h m3 m4 12.1k 1% f in freq = 220khz sense2 C pgnd2 v fb2 fcb i on2 i th2 extlpf track1 sgnd v rng1 v rng2 bg2 c ss 0.1f 0.01f 0.047f 470pf 150pf 1000pf 56pf 150pf 1000pf r on2 1.1m 1000pf m1, m2: renesas hat2168h m3, m4: renesas hat2165h c out1 : sanyo poscap 4tpd330m c out2 : sanyo poscap 2r5tpd470m c in : taiyo yuden: tmk325bj106km db1, db2: cmdsh-3 l1: panasonic etqp3h1r4bf l2: panasonic etqp2h1r2bf 15k 6.04k 1% 470pf 3708 f17 v out2 1.8v 15a c out2 470f 2.5v s 2 c in 10f 25v s 6 v in 7v to 24v + + + figure 17. high ef? ciency, dual output power supply with external frequency synchronization
ltc3708 28 3708fb typical applications v cc 5v 5v track1 boost2 bat54a boost1 ltc3708euh tg1 v rng1 i on1 extlpf i th1 v fb1 track2 0 0 boost1 0 0 1.2m 59k 1nf 1nf sense1 + sense1 C run/ss sgnd pgnd1 bg1 fcb drv cc sw1 tg2 v cc v cc v rng2 i on2 intlpf i th2 v fb2 pwrgd boost2 sense2 + sense2 C pgnd2 bg2 sw2 0.22f 0.22f 100pf c2 10f 25v v in 604k 30.9k v in v cc v cc si4860dy si4860dy si4860dy l2 2.2h c3 10f 25v c4 10f 25v si4860dy c out1 470f 2.5v b240a l1 2.2h 1f 10 * c1 10f 25v 100pf 1nf 1nf 15k 15k 10k 10k 10k 1% 10k 1% 100k 5v 100pf 150pf 150pf 0.1f v in * 1m 9.09k 10nf 3708 ta03 470pf 100pf 100pf 12.1k 1% 30.1k 1% 10k 1% 6.04k 1% + 1.8v 6a 9v to 20v gnd gnd sgnd run/ss 2.2f 2.2f boost2 2.2f 6.3v x5r v in 0 0 b240a b240a c out2 470f 2.5v + gnd pgood 0.9v 4a *signal ground, routed separately c out1 , c out2 : sanyo 2r5tpd470m c1 to c4: taiyo yuden tmk325bj106mm l1, l2: sumida cdep105-2r2mc-88 ddr ii supplies with transient coupling
ltc3708 29 3708fb typical applications dual-phase, 30a power supply with 10mv output ripple 1f 0.22f boost2 bat54a 10 pgnd2 1f pgnd1 1f tg1 0.01f 220pf 220pf c in1 : sanyo os-con 6svp100m c out3 , c out4 : sanyo poscap 2r5tpd470m l1, l2: panasonic etqp4lr19 m1 to m4: renesas hat2165 v in pgood 100k boost1 sw1 sense1 + bg1 sense1 C pgnd1 v rng1 i on1 v fb1 track2 extlpf i th1 v cc track1 fcb drv cc ltc3708 tg2 boost2 boost2 sw2 sense2 + 0.22f m2 m1 v out 1v 30a v in l1 0.19h l2 0.19h b340a m3 m4 sense2 C pgnd2 v rng2 v rng1 v fb2 i on2 pwrgd intlpf i th2 run/ss sgnd bg2 1000pf 0.01f v cc 274k v cc r1 10k 0.1% r2 15k 0.1% 22k 100k 10k 274k v in 0.01f 1nf 3708 ta05 100pf c out4 470f 2.5v s 2 c out2 1f 6.3v v cc b340a c out3 470f 2.5v s 2 c in1 100f 6.3v c in2 -c in7 4.7f 6.3v s 6 v in 5v track c out1 1f 6.3v 100pf + 22.1k 100k + +
ltc3708 30 3708fb typical applications 12v/12a and 5v/12a at 300khz application v cc 5v 5v track1 boost2 bat54a boost1 ltc3708euh tg1 v rng1 i on1 extlpf i th1 v fb1 track2 boost1 5.6m 0 0 88.7k 1nf 1nf sense1 + sense1 C run/ss sgnd pgnd1 bg1 fcb drv cc sw1 tg2 v cc v rng2 i on2 intlpf i th2 v fb2 pgood boost2 sense2 + sense2 C pgnd2 bg2 sw2 100pf 0.1f q1 hat2167h q2 hat2167h b340la v in 2.2m 88.7k v in v cc v cc q3 hat2167h q4 hat2167h l2 2.4h c out1 150f 16v s 2 l1 3.5h c6 1f 10 c3 3.3f 50v x5r c4 3.3f 50v x5r 2.2nf 1.5nf 33.2k 15k 24.9k 24.9k 10k 75k 100k 5v 47pf 150pf 150pf 0.1f 5.11k 22nf 3708 ta04 470pf 22pf 191k 75k 10k 10k 22pf + v out1 12v 12a v in 20v to 28v 2.2f boost2 100pf 0 0 0 0 47pf c out2 220f 6.3v s 2 + pgood v out2 5v 12a c out1 : sanyo 16svp150m c out2 : sanyo 6tpd220m c1 to c6: tdk c4532x5r1h335m l1: sumida cdep147-3r5mc-h l2: sumida cdep147-2r4mc 0.1f c2 3.3f 50v x5r c1 3.3f 50v x5r c6 3.3f 50v x5r c5 3.3f 50v x5r d3 b340la 100f 50v +
ltc3708 31 3708fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05
ltc3708 32 3708fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1207 rev b ? printed in usa related parts typical application area = 650mm 2 , height = 3mm v cc 5v 5v track1 boost2 bat54a boost1 ltc3708euh tg1 v rng1 i on1 extlpf i th1 v fb1 track2 boost1 1m 100k 1000pf 1000pf sense1 + sense1 C run/ss sgnd sgnd pgnd1 bg1 fcb drv cc sw1 tg2 v cc v rng2 i on2 intlpf i th2 v fb2 pgood boost2 sense2 + sense2 C pgnd2 bg2 sw2 0.1f 0.1f q1a si4816bdy q1b si4816bdy v in 750k 100k v in v cc v cc q2a si4816bdy q2b si4816bdy l2 1.8h c11 10f 25v c1 150f 4v c16 100f 6.3v l1 1.8h 1f 10 c9 10f 25v 560pf 560pf 20k 15k 20k 20k 10k 20k 100k 5v 220pf 150pf 150pf 0.1f v in bat54w 220pf 5.11k 22nf 3708 ta06 470pf 220pf 220pf 31.6k 20k 10k 10k + v out1 2.5v 5a v in 7v to 24v sgnd run/ss 1f 1f boost2 2.2f 6.3v c13 150f 4v + pgood v out2 1.8v 5a c15 100f 6.3v c1, c13: sanyo 4tpe150mazb c9, c11: taiyo yuden tmk325bj106km c15, c16: tdk c3225x5r0j107m l1, l2: toko fdv0630-1r8m part number description comments ltc1778 wide operating range, no r sense step-down controller single channel, gn16 package ltc3709 2-phase, no r sense step-down controller with tracking/sequencing single output, remote sensing ltc3728 dual, 550khz, 2-phase synchronous step-down switching regulator fixed frequency, dual output ltc3729 550khz, polyphase ? , high ef? ciency, synchronous step-down switching regulator fixed frequency, single output, up to 12-phase operation ltc3731 3-phase, 600khz, synchronous buck switching regulator controller 3-phase, single output ltc3778 wide operating range, no r sense step-down controller single channel, separate v on programming polyphase is a registered trademark of linear technology corporation

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